A microcomputer 1 having a construction as shown in FIG. 8 is known for switching the operation mode of a microcomputer between a normal operation mode and each of various kinds of test modes for testing the functions of respective parts. The microcomputer 1 includes a plurality of operation mode selecting terminals 2, and an internal mode decoder 3 for decoding the level setting states of the terminals to set the operation mode. However, during normal microcomputer 1 operation, the number of unusable terminals is increased; thereby needlessly increasing the chip size of the microcomputer.
Therefore, under such a situation, a microcomputer 4 having a construction as shown in FIG. 9 is provided. According to the construction of the microcomputer 4, a mode decoder 6 executes a decoding operation when the microcomputer 4 is released from a reset state based upon an external signal received at the reset terminal 5 of the microcomputer 4 to determine an operation mode. The selection terminal 2 is then set to be usable as an input terminal or output terminal.
In certain applications in which the microcomputer is mounted on a printed board, it is sufficient to make only power on reset effective. In this case, the signal level of a reset terminal 5 is fixed to a high or low level so that the reset terminal 5 is inactive. Accordingly, when the microcomputer 4 shown in FIG. 9 is applied to such an application as described above, the operation mode of the microcomputer 4 cannot be altered. For example, if the reset terminal 5 is pulled up or pulled down, the potential of the reset terminal can be varied by a switch or the like. However, in this case, there is a disadvantage that the resistance amount to noises is lowered. Therefore, when electrostatic discharge or the like occurs, it is difficult to reset the microcomputer.
Furthermore, for example, JP-A-2001-273274 discloses a construction in which the signal level of a reset terminal is monitored when the power-on-reset in the microcomputer is released, and the normal mode and the test mode are switched in accordance with the level thereof (high or low).
Even in the technique disclosed by the above publication, in order to switch the operation mode when the microcomputer is mounted on the printed board, it is required that power-on-reset be temporarily active. Therefore, during operation of the microcomputer in a test mode, it is impossible to switch the present test mode to the next test mode while the power is on. Accordingly, the microcomputer is required to be turned on again every time the test pattern is switched when a plurality of test patterns are continuously executed. That is, this technique is inconvenient because it requires more time to carry out the test.